48 Gbit∕s InP DHBT MS-DFF with very low time jitter
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/el_20020777?crawler=true&mimetype=application/pdf
Reference7 articles.
1. 45 Gbit/s decision IC module using InAlAs/InGaAs/InP HEMTs
2. 40 Gbit/s decision IC using InP/InGaAs composite-collector heterojunction bipolar transistors
3. 40 Gbit∕s master-slave D-type flip-flop in InP DHBT technology
4. High-input-sensitivity, low-power 43 Gbit∕s decision circuit using InP∕InGaAs DHBTs
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Low-power high-speed performance of current-mode logic D flip-flop topology using negative-differential-resistance devices;IET Circuits, Devices & Systems;2008
2. A 50-Gbit/s 450-mW Full-Rate 4:1 Multiplexer With Multiphase Clock Architecture in 0.13-$\mu{\hbox {m}}$ InP HEMT Technology;IEEE Journal of Solid-State Circuits;2007-03
3. 43 Gb/s decision circuits in InP DHBT technology;IEEE Microwave and Wireless Components Letters;2004-01
4. 40 Gbit/s transmission: III–V integrated circuits for opto-electronic interfaces;Annales Des Télécommunications;2003-09
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