Low-power high-speed performance of current-mode logic D flip-flop topology using negative-differential-resistance devices
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering,Control and Systems Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/iet-cds_20070135?crawler=true&mimetype=application/pdf
Reference20 articles.
1. 48 Gbit∕s InP DHBT MS-DFF with very low time jitter
2. Design of high-speed master-slave D-type flip-flop in InP DHBT technology
3. A 80-gbit/s D-type flip-flop circuit using InP HEMT technology
4. A 2.5-V 45-Gb/s decision circuit using SiGe BiCMOS logic
5. High-frequency CML clock dividers in 0.13-/spl mu/m CMOS operating up to 38 GHz
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