Energy‐efficient higher‐side‐reset‐and‐set switching scheme for SAR ADC
Author:
Affiliation:
1. The School of MicroelectronicsXi'an Jiaotong UniversityXi'an710049People's Republic of China
Funder
National Natural Science Foundation of China
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2017.2186
Reference5 articles.
1. A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure
2. A 0.3 V 10‐bit 1.17 f SAR ADC with merge and split switching in 90 nm CMOS;Lin J.‐Y.;Trans. Circuits Syst. I Regul. Pap.,2015
3. A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS
4. A 0.4 V 1.94 fJ/conversion‐step 10 bit 750 kS/s SAR ADC with input‐range‐adaptive switching;Lee P.C.;Trans. Circuits Syst. I Regul. Pap.,2016
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