Design and evaluation of a novel enhancement mode FET logic gate configuration in AlGaAs/GaAs/AlGaAs quantum well HEMT technology-Reference-Cited by-同舟云学术

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Design and evaluation of a novel enhancement mode FET logic gate configuration in AlGaAs/GaAs/AlGaAs quantum well HEMT technology

Published:1997 Issue:4 Volume:144 Page:243
ISSN:1350-2409
Container-title:IEE Proceedings - Circuits, Devices and Systems
language:en
Short-container-title:IEE Proc., Circuits Devices Syst.

Author:

Bushehri E.,Thiede A.,Bratov V.,Staroselsky V.,Rieger-Motzer M.,Huelsmann A.,Schlichter T.,Raynor B.

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Link

https://digital-library.theiet.org/content/journals/10.1049/ip-cds_19971145?crawler=true&mimetype=application/pdf

Reference7 articles.

1. E-Beam Direct-Write in a Dry-Etched Recess Gate HEMT Process for GaAs/AlGaAs Circuits

2. 16×16 bit parallel multiplier based on 6 K gate array with 0.3 μm AlGaAs/GaAs quantum well transistors

3. Berroth, M.: ‘IAF design manual, active devices’, Version 3.0 1994 March), p. 4.1–4.27

4. Eliminating threshold losses in MOS circuits by bootstrapping using varactor coupling

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A voltage-controlled ring oscillator using InP full enhancement-mode HEMT logic;Journal of Semiconductors;2009-03

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