From static ternary adders to high‐performance race‐free dynamic ones

Author:

Rezaie Shirin1,Faghih Mirzaee Reza2ORCID,Navi Keivan3,Hashemipour Omid3

Affiliation:

1. Department of Computer EngineeringScience and Research Branch, Islamic Azad UniversityTehranIran

2. Department of Computer EngineeringShahr‐e‐Qods BranchIslamic Azad UniversityTehranIran

3. Faculty of Electrical and Computer EngineeringShahid Beheshti University, G.C.TehranIran

Publisher

Institution of Engineering and Technology (IET)

Subject

General Engineering,Energy Engineering and Power Technology,Software

Reference28 articles.

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3. NigussieE.E.: ‘Exploration and design of high performance variation tolerant on‐chip interconnects’. PhD thesis University of Turku 2010

4. Multiple‐valued logic buses for reducing bus energy in low‐power systems;Ozer E.;IEE Proc. Comput. Digit. Tech.,2006

5. DubrovaE.: ‘Multiple‐valued logic in VLSI: challenges and opportunities’.Proc. NORCHIP 1999 pp.340–350

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