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Resilience and yield of flip‐flops in future CMOS technologies under process variations and aging

  • Published:2014-01 Issue:1 Volume:8 Page:19-26
  • ISSN:1751-858X
  • Container-title:IET Circuits, Devices & Systems
  • language:en
  • Short-container-title:IET Circuits, Devices & Systems

Author:

Werner Christoph1,Backs Benedikt1,Wirnshofer Martin1,Schmitt‐Landsiedel Doris1

Affiliation:

1. Lehrstuhl Technische ElektronikTechnical University MunichTheresienstr.90Muenchen80290Germany

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Control and Systems Engineering

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Impacts of Process Variations and Aging on Lifetime Reliability of Flip-Flops;Lifetime Reliability-aware Design of Integrated Circuits;2022-11-17

2. Restructuring-Based Lifetime Reliability Improvement of Nanoscale Master-Slave Flip-Flops;Lifetime Reliability-aware Design of Integrated Circuits;2022-11-17

3. Timing Reliability Improvement of Master-Slave Flip-Flops in the Presence of Aging Effects;IEEE Transactions on Circuits and Systems I: Regular Papers;2020-12

4. Impacts of Process Variations and Aging on Lifetime Reliability of Flip-Flops: A Comparative Analysis;IEEE Transactions on Device and Materials Reliability;2019-09

5. Reversible logic‐based image steganography using quantum dot cellular automata for secure nanocommunication;IET Circuits, Devices & Systems;2017-01
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