PLL architecture with a composite PFD and variable loop filter
Author:
Affiliation:
1. Department of Electronics and Communication EngineeringMEA Engineering CollegeVengoor PostMalappuramKeralaIndia
2. Department of ElectronicsIndian Institute of Information Technology Design and Manufacturing (IIITDM) KancheepuramChennaiIndia
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering,Control and Systems Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2017.0336
Reference21 articles.
1. Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops
2. Ismail N.M.H. Othman M.: ‘CMOS phase frequency detector for high speed applications’.Proc. IEEE Int. Conf. (ICM) Conf. December2009 pp.201–204
3. Phase Frequency Detector With Minimal Blind Zone for Fast Frequency Acquisition
4. A Novel Phase Frequency Detector for a High Frequency PLL Design
5. Low power, high frequency, free dead zone PFD for a PLL design
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