Built‐in self‐test structure for fault detection of charge‐pump phase‐locked loop-Reference-Cited by-同舟云学术

Built‐in self‐test structure for fault detection of charge‐pump phase‐locked loop

Published:2016-07 Issue:4 Volume:10 Page:317-321
ISSN:1751-858X
Container-title:IET Circuits, Devices & Systems
language:en
Short-container-title:IET Circuits, Devices & Systems

Author:

Xia Lanhua¹²,Wu Jianhui¹²,Huang Cheng¹,Zhang Meng¹

Affiliation:

1. National ASIC System Engineering Research CenterSoutheast UniversityNanjingJiangsu Province210096People's Republic of China

2. Jiangsu Provincial Key Laboratory of Sensor Network TechnologySoutheast UniversityNanjing210096People's Republic of China

Funder

National Natural Science Foundation of China

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Control and Systems Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2015.0224

Reference22 articles.

1. An Embedded All-Digital Circuit to Measure PLL Response

2. Hsiao S.‐W. Tzou N. Chatterjee A.: ‘A programmable BIST design for PLL static phase offset estimation and clock duty cycle detection’.IEEE 31st VLSI Test Symp. (VTS) 2013 pp.1–6

3. Dasnurkar S.D. Abraham J.A.: ‘PLL lock time prediction and parametric testing by lock waveform characterization’.IEEE 16th Int. Mixed‐Signals Sensors and Systems Test Workshop 2010 pp.1–5

4. Hsiao S.‐W. Wang X. Chatterjee A.: ‘Analog sensor based testing of phase‐locked loop dynamic performance parameters’.The 22nd Asian Test Symp. (ATS) 2013 pp.50–55

5. On-Chip Measurement of Jitter Transfer and Supply Sensitivity of PLL/DLLs

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1. Novel Power-Efficient Fast-Locking Phase-Locked Loop Based on Adaptive Time-to-Digital Converter-Aided Acceleration Compensation Technology;Electronics;2024-09-10

2. Fault-based Built-in Self-test and Evaluation of Phase Locked Loops;ACM Transactions on Design Automation of Electronic Systems;2021-05-31

3. All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops;IET Circuits, Devices & Systems;2020-12-10

4. A self-refereed design-for-test structure of CP-PLL for on-chip jitter measurement;IEICE Electronics Express;2018