16‐bit 1‐MS/s SAR ADC with foreground digital‐domain calibration
Author:
Affiliation:
1. Shanghai Jiao Tong University800 Dongchuan Road, MinhangShanghai200240People's Republic of China
Funder
National Natural Science Foundation of China
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering,Control and Systems Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2017.0412
Reference29 articles.
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2. A self-calibrating 15 bit CMOS A/D converter
3. A Digital-Domain Calibration of Split-Capacitor DAC for a Differential SAR ADC Without Additional Analog Circuits
4. Liu W. Huang P. Chiu Y.: ‘A 12‐bit 50‐MS/s 3.3‐mW SAR ADC with background digital calibration’.Proc. IEEE CICC September.2009 pp.1–4
5. Morie T. Miki T. Matsukawa K. et al.: ‘A 71dB‐SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise’.Proc. ISSCC Digest of Technical Papers February.2013 pp.272–273
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