Accelerating low‐voltage SAR ADC operation via comparator timing assisted and circuit adaptive tuning techniques
Author:
Affiliation:
1. Department of Electrical and Computer EngineeringSouthern Illinois UniversityCarbondale62901USA
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering,Control and Systems Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2019.0374
Reference25 articles.
1. An Energy-Efficient Time-Domain Asynchronous 2 b/Step SAR ADC With a Hybrid R-2R/C-3C DAC Structure
2. An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC
3. An 8 bit 0.3–0.8 V 0.2–40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS
4. A 400-MS/s 10-b 2-b/Step SAR ADC With 52-dB SNDR and 5.61-mW Power Dissipation in 65-nm CMOS
5. A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS
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