Precision analysis with analytical bit‐width optimisation process for linear circuits with feedbacks-Reference-Cited by-同舟云学术

Precision analysis with analytical bit‐width optimisation process for linear circuits with feedbacks

Published:2018-06-15 Issue:5 Volume:12 Page:563-570
ISSN:1751-858X
Container-title:IET Circuits, Devices & Systems
language:en
Short-container-title:IET Circuits, Devices & Systems

Author:

Lamini El‐Sedik¹²,Tagzout Samir³,Belbachir Hacène¹,Belouchrani Adel⁴

Affiliation:

1. USTHB, Faculty of MathematicsRECITS LaboratoryBP 32, El Alia 16111, Bab EzzouarAlgiersAlgeria

2. Division de Microélectronique et NanotechnologieCentre de Développement des Technologies Avancées, CDTAAlgiersAlgeria

3. Groupe Brandt, Pôle Industrie, CEVITAL, Garidi IIKouba 16005AlgeirsAlgeria

4. Electrical Engineering Department Ecole Nationale PolytechniqueLDCCPBP 16028, El HarrachAlgiersAlgeria

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Control and Systems Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2017.0514

Reference26 articles.

1. An efficient hybrid engine to perform range analysis and allocate integer bit-widths for arithmetic circuits

2. Accuracy-Guaranteed Bit-Width Optimization

3. Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory

4. Radecka K. Zilic Z.: ‘Using arithmetic transform for verification of datapath circuits via error modeling’.Proc. IEEE VLSI Test Symp May2000 pp.271–277

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