Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory-Reference-Cited by-同舟云学术

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Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory

Published:2010-03 Issue:3 Volume:29 Page:405-413
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Kinsman Adam B.,Nicolici Nicola

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx5/43/5419222/05419231.pdf?arnumber=5419231

Cited by 27 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. HECATE: Performance-Aware Scale Optimization for Homomorphic Encryption Compiler;2022 IEEE/ACM International Symposium on Code Generation and Optimization (CGO);2022-04-02

2. Computing Integer Bit Widths for Video Codec Implementations;2021 Picture Coding Symposium (PCS);2021-06

3. An Overflow/Underflow-Free Fixed-Point Bit-Width Optimization Method for OS-ELM Digital Circuit;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2021

4. AIOSC: Analytical Integer Word-length Optimization Based on System Characteristics for Recursive Fixed-Point Linear Time Invariant Systems;International Journal of Engineering;2020-07

5. Arithmetic Approaches for Rigorous Design of Reliable Fixed-Point LTI Filters;IEEE Transactions on Computers;2020-04-01

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