Ultra‐low‐voltage GDI‐based hybrid full adder design for area and energy‐efficient computing systems

Author:

Sanapala Kishore1,Sakthivel Ramachandran1ORCID

Affiliation:

1. School of Electronics EngineeringVIT UniversityVellore632014India

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Control and Systems Engineering

Cited by 35 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design of Low Power and High Speed 1-bit Full Adder for DSP Applications;2024 International Conference on Advancements in Power, Communication and Intelligent Systems (APCI);2024-06-21

2. Design and analysis of 1-bit hybrid full adder cells for fast computation;International Journal of Electronics;2024-06-03

3. A novel low-power full swing hybrid full adder-based 7:3 counter for MBW multiplier;Sādhanā;2024-05-30

4. Performance Evaluation of various CMOS designs for Signal Processing Applications;2024 5th International Conference for Emerging Technology (INCET);2024-05-24

5. FPGA Implementation and Optimization of Adder Performance with Hybrid FinFET-GDI Logic;2024 International Conference on Electronics, Computing, Communication and Control Technology (ICECCC);2024-05-02

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