Bulk-drain connected load for subthreshold MOS current-mode logic

Author:

Cannillo F.,Toumazou C.,Lande T.S.

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

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3. A Mixed-Signal Structured AdEx Neuron for Accelerated Neuromorphic Cores;IEEE Transactions on Biomedical Circuits and Systems;2018-10

4. Design and development of high performance MOS current mode logic (MCML) processor for fast and power efficient computing;Cluster Computing;2018-02-15

5. A Novel Bulk Drain Connected 6T SRAM Cell;Communications in Computer and Information Science;2017

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