Device and circuit performance analysis of double gate junctionless transistors at L g = 18 nm-Reference-Cited by-同舟云学术

Device and circuit performance analysis of double gate junctionless transistors at L g = 18 nm

Published:2014-03 Issue:3 Volume:2014 Page:105-110
ISSN:2051-3305
Container-title:The Journal of Engineering
language:en
Short-container-title:J. eng.

Author:

Sahu Chitrakant¹,Singh Jawar¹

Affiliation:

1. Department of Electronics and Communication EngineeringPDPM Indian Institute of Information Technology, Design and Manufacturing JabalpurMadhya PradeshIndia

Publisher

Institution of Engineering and Technology (IET)

Subject

General Engineering,Energy Engineering and Power Technology,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/joe.2013.0269

Reference24 articles.

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3. Double‐gate silicon‐on‐insulator transistor with volume inversion: a new device with greatly performance;Balestra F.;IEEE Electron Device Lett.,1987

4. Nanowire transistors without junctions;Colinge J.P.;Nat. Nanotechnol.,2010

5. Electrical characteristics of 20‐nm junctionless Si nanowire transistors;Park C.‐H.;Solid State Electron.,2012

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