Mitigating information leakage during critical communication using S*FSM-Reference-Cited by-同舟云学术

Mitigating information leakage during critical communication using S*FSM

Published:2019-03-20 Issue:4 Volume:13 Page:292-301
ISSN:1751-8601
Container-title:IET Computers & Digital Techniques
language:en
Short-container-title:IET Computers & Digital Techniques

Author:

Borowczak Mike¹^ORCID,Vemuri Ranga²

Affiliation:

1. Department of Computer ScienceCollege of Engineering and Applied ScienceUniversity of WyomingWyomingUSA

2. Department of Electrical Engineering and Computer ScienceCollege of Engineering and Applied ScienceUniversity of CincinnatiOhioUSA

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2018.5186

Reference42 articles.

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2. Tiri K. Verbauwhede I.: ‘A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation’.Proc. Design Automation and Test in Europe Conference and Exhibition Paris France 2004 pp.246–251

3. Sundaresan V. Rammohan S. Vemuri R.: ‘Power invariant secure IC design methodology using reduced complementary dynamic and differential logic’.IFIP Int. Conf. Very Large Scale Integration (VLSI – SoC 2007) Atlanta GA USA 2007 pp.1–6

4. Ramakrishnan L.N. Chakkaravarthy M. Manchanda A.S. et al.: ‘SDMLp: on the use of complementary pass transistor logic for design of DPA resistant circuits’.2012 IEEE Int. Symp. Hardware‐Oriented Security and Trust (HOST) San Francisco CA USA 2012

5. Extended Finite State Machine

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1. FSMx-Ultra: Finite State Machine Extraction From Gate-Level Netlist for Security Assessment;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11

2. FSMx: Finite State Machine Extraction from Flattened Netlist With Application to Security;2022 IEEE 40th VLSI Test Symposium (VTS);2022-04-25

3. S*FSMs for Reduced Information Leakage: Power Side Channel Protection Through Secure Encoding;Behavioral Synthesis for Hardware Security;2021-05-28

4. SD‐SHO: Security‐dominated finite state machine state assignment technique with a satisfactory level of hardware optimization;IET Computers & Digital Techniques;2021-04-21