SDMLp: On the use of complementary Pass transistor Logic for design of DPA resistant circuits-Reference-Cited by-同舟云学术

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SDMLp: On the use of complementary Pass transistor Logic for design of DPA resistant circuits

Published:2012-06 Issue: Volume: Page:
ISSN:
Container-title:2012 IEEE International Symposium on Hardware-Oriented Security and Trust
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Author:

Ramakrishnan Lakshmi Narasimhan,Chakkaravarthy Manoj,Manchanda Antarpreet Singh,Borowczak Mike,Vemuri Ranga

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/6218991/6224308/06224315.pdf?arnumber=6224315

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2. Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation;IEEE Journal on Emerging and Selected Topics in Circuits and Systems;2021-06

3. S*FSMs for Reduced Information Leakage: Power Side Channel Protection Through Secure Encoding;Behavioral Synthesis for Hardware Security;2021-05-28

4. DGFinSAL: A New Low Power Adiabatic FinFET-Based Logic Family for DPA-Resistant Applications;Circuits, Systems, and Signal Processing;2021-03-27

5. Path-Balanced Logic Design to Realize Block Ciphers Resistant to Power and Timing Attacks;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2019-05

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