Reliability‐aware simultaneous multithreaded architecture using online architectural vulnerability factor estimation-Reference-Cited by-同舟云学术

Reliability‐aware simultaneous multithreaded architecture using online architectural vulnerability factor estimation

Published:2015-03 Issue:2 Volume:9 Page:124-133
ISSN:1751-8601
Container-title:IET Computers & Digital Techniques
language:en
Short-container-title:IET Computers & Digital Techniques

Author:

Pouyan Fatemeh¹,Azarpeyvand Ali¹²^ORCID,Safari Saeed¹,Fakharie Sied Mehdi¹

Affiliation:

1. Nanoelectronics Center of ExcellenceSchool of Electrical and Computer EngineeringUniversity of TehranNorth Kargar AvenueTehran14395‐515Islamic Republic of Iran

2. Department of Computer EngineeringUniversity of ZanjanZanjanIslamic Republic of Iran

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2013.0162

Reference24 articles.

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2. Characterization of soft errors caused by single event upsets in CMOS processes

3. Mukherjee S.S. Weaver C.T. Emer J.S. Reinhardt S.K. Austin T.M.: ‘A systematic methodology to compute the architectural vulnerability factors for a high‐performance microprocessor’.MICRO ACM/IEEE 2003 pp.29–42

4. Fu X. Li T. Fortes J.A.B.: ‘Sim‐soda: a unified framework for architectural level software reliability analysis’.Workshop on modeling benchmarking and Simulation in conjunction with ISCA 2006

5. Wang N.J. Mahesri A. Patel S.J.: ‘Examining ACE analysis reliability estimates using fault‐injection’.Proc. 34th Int. Symp. on Computer Architecture (34th ISCA'07) ACM SIGARCH San Diego California USA 2007 pp.460–469

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4. Erratum;IET Computers & Digital Techniques;2015-07