Morphable hundred‐core heterogeneous architecture for energy‐aware computation

Author:

Neves Nuno1,Mendes Henrique1,Chaves Ricardo Jorge1,Tomás Pedro1,Roma Nuno1

Affiliation:

1. INESC‐IDInstituto Superior TécnicoUniversidade de LisboaRua Alves Redol, 91000‐029LisboaPortugal

Funder

Fundação para a Ciência e a Tecnologia

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference28 articles.

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3. Semeraro G. Magklis G. Balasubramonian R. Albonesi D. Dwarkadas S. Scott M.: ‘Energy‐efficient processor design using multiple clock domains with dynamic voltage and frequency scaling’.Eighth Int. Symp. on High‐Performance Computer Architecture (ISCA) February2002 pp.29–40

4. Muthukaruppan T.S. Pricopi M. Venkataramani V. Mitra T. Vishin S.: ‘Hierarchical power management for asymmetric multi‐core in dark silicon era’.Proc. of the 50th Annual Design Automation Conf. 2013 pp.174:1–174:9

5. Zhu Y. Reddi V.: ‘High‐performance and energy‐efficient mobile web browsing on big/little systems’.2013 IEEE 19th Int. Symp. on High Performance Computer Architecture (HPCA) February2013 pp.13–24

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