On‐chip communication for neuro‐glia networks

Author:

Martin George1,Harkin Jim1,McDaid Liam J.1,Wade John J.1,Liu Junxiu1

Affiliation:

1. School of Computing, Engineering and Intelligent SystemsUlster UniversityMageeDerryNorthern Ireland

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference38 articles.

1. Scalable hierarchical network‐on‐chip architecture for spiking neural network hardware implementations;Carrillo S.;IEEE Trans. Parallel Distrib. Syst.,2013

2. De Lima F.G. Cota E. Carro L. et al.: ‘Designing a radiation hardened 8051‐like micro‐controller’.Proc. – 13th Symp. Integrated Circuits Systems Design Manaus 2000 pp.255–260

3. Rebaudengo M. Sterpone L. Violante M. et al.: ‘Combined software and hardware techniques for the design of reliable IP processors’.Proc. – IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems Arlington VA October2006 pp.265–273

4. Zhang S. Liu H.: ‘Synthetical analysis on space radiation tolerance techniques in ASICs and FPGAs’.2011 Int. Conf. System Science Engineering Design and Manufacturing Informatization. ICSEM 2011 Guiyang 2011 vol. 2 pp.305–310

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