Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations-Reference-Cited by-同舟云学术

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Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations

Published:2013-12 Issue:12 Volume:24 Page:2451-2461
ISSN:1045-9219
Container-title:IEEE Transactions on Parallel and Distributed Systems
language:
Short-container-title:IEEE Trans. Parallel Distrib. Syst.

Author:

Carrillo Snaider,Harkin Jim,McDaid Liam J.,Morgan Fearghal,Pande Sandeep,Cawley Seamus,McGinley Brian

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Signal Processing

Link

http://xplorestaging.ieee.org/ielx5/71/6648551/06322959.pdf?arnumber=6322959

Cited by 85 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Unidirectional and hierarchical on-chip interconnected architecture for large-scale hardware spiking neural networks;Neurocomputing;2024-12

2. Neuron grouping and mapping methods for 2D-mesh NoC-based DNN accelerators;Journal of Parallel and Distributed Computing;2024-11

3. FPGA-Based Spiking Neural Networks;Recent Advances in Neuromorphic Computing [Working Title];2024-08-09

4. Photonics for Neuromorphic Computing: Fundamentals, Devices, and Opportunities;Advanced Materials;2024-07-16

5. AnSpiCS-Net: Reconfigurable Network-on-Chip for Analog Spiking Recurrent Neural Networks;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

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