Methodology for adapting on‐chip interconnect architectures-Reference-Cited by-同舟云学术

Methodology for adapting on‐chip interconnect architectures

Published:2014-05 Issue:3 Volume:8 Page:109-117
ISSN:1751-8601
Container-title:IET Computers & Digital Techniques
language:en
Short-container-title:IET Computers & Digital Techniques

Author:

Suboh Suboh¹,Narayana Vikram²,Bakhouya Mohamed³,Gaber Jaafar⁴,El‐Ghazawi Tarek²

Affiliation:

1. Electrical Engineering and Computer ScienceUniversity of Central FloridaUCFUSA

2. Electrical and Computer Engineering Dept.The George Washington UniversityGWUUSA

3. International University of RabatMorocco

4. Universite de Technologie de Belfort/MontbeliardFrance

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2013.0021

Reference32 articles.

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3. Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures

4. Kumar S. Jantsch A. Soininen J.‐P. et al.: ‘A network on chip architecture and design methodology’.IEEE Computer Society Annual Symp. VLSI (ISVLSI) 2002 pp.105–112

5. Bononi L. Concer N.: ‘Simulation and analysis of network on chip architectures: ring spidergon and 2D mesh’.Conf. Design Automation and Test in Europe 2006 pp.154–159

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