Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex‐5 field‐programmable gate array-Reference-Cited by-同舟云学术

Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex‐5 field‐programmable gate array

Published:2018-03-15 Issue:4 Volume:12 Page:150-157
ISSN:1751-8601
Container-title:IET Computers & Digital Techniques
language:en
Short-container-title:IET Computers & Digital Techniques

Author:

Olivito Javier¹,Serrano Felipe²,Clemente Juan Antonio²,Mecha Hortensia²,Resano Javier¹

Affiliation:

1. Department of Computer Science and Systems EngineeringUniversity of ZaragozaZaragoza50018Spain

2. Departamento de Arquitectura de Computadores y AutomáticaComplutense University of MadridMadrid28040Spain

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2016.0095

Reference37 articles.

1. Becker T. Luk W. Cheung P.Y.K.: ‘Energy‐aware optimization for run‐time reconfiguration’.Field‐Programmable Custom Computing Machines 2010 pp.55–62

2. Achieving energy efficiency through runtime partial reconfiguration on reconfigurable systems

3. Dynamic power optimization by exploiting self-reconfiguration in Xilinx Spartan 3-based systems

4. Lehn D.I. Puttegowda K. Park J.H. et al.: ‘Evaluation of rapid context switching on a CSRC device’.Proc. of the Int. Conf. of Engineering of Reconfigurable Systems and Algorithms (ERSA) 2002 pp.209–215

5. Hartenstein R.: ‘A decade of reconfigurable computing: a visionary retrospective’.Proc. of the Conf. Design Automation and Test in Europe (DATE) 2001 pp.642–649

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