Partitioned security processor architecture on FPGA platform

Author:

Paul Rourab1,Shukla Sandeep1

Affiliation:

1. Computer Science Engineering DepartmentIndian Institute of Technology KanpurIndia

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference48 articles.

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2. Chen X. Dick R.P. Choudhary A.: ‘Operating system controlled processor‐memory bus encryption’.Design Automation and Test in Europe Munich Germany March2008 pp.1154–1159

3. Wang Z. Lee R.B.: ‘A novel cache architecture with enhanced performance and security’.41st IEEE/ACM Int. Symp. on Microarchitecture November2008 pp.83–93

4. Brickell E. Graunke G. Neve M. et al.: ‘Software mitigations to hedge AES against cache‐based software side channel vulnerabilities’ 2006

5. Broadwell P. Harren M. Sastry N.: ‘SCRASH: a system for generating secure crash information’.Proc. 12th Conf. on USENIX Security Symp. (SSYM'03) USENIX Association Berkeley CA USA 2003 vol. 12 p.19

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