Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA-Reference-Cited by-同舟云学术

Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA

Published:2021-04-04 Issue:5 Volume:15 Page:349-361
ISSN:1751-8601
Container-title:IET Computers & Digital Techniques
language:en
Short-container-title:IET Computers & Digital Techniques

Author:

Gupta Mangal D.¹,Chauhan Rajeev K.¹

Affiliation:

1. Department of Electronics and Communication Engineering MMMUT Gorakhpur Uttar Pradesh India

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/cdt2.12027

Reference28 articles.

1. An algorithm and architecture for non‐recursive pseudorandom sequence generation using sequence folding technique;Soundra Pandian K.K.;Intl. J. Comput. Appl.,2017

2. Chaos-Based Bitwise Dynamical Pseudorandom Number Generator On FPGA

3. High‐performance elliptic curve cryptography processor over NIST prime fields

4. Throughput/area optimised pipelined architecture for elliptic curve crypto processor

5. Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA

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