Diode triggered ESD power clamp circuit with accurate discharge duration
Author:
Affiliation:
1. School of Automation and Information EngineeringXi'an University of TechnologyXi'an710048People's Republic of China
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2016.0167
Reference7 articles.
1. ESD
2. Enhanced ESD power clamp for antenna switch controller with SOI CMOS technology
3. Two ESD detection circuits for 3 × VDD tolerant I/O buffer in low‐voltage CMOS processes with low leakage currents;Liu H.X.;IEEE Trans. Device Mater. Reliab.,2013
4. An area‐efficient clamp based on transmission gate feedback technology for power rail electrostatic discharge protection;Cai X.;IEEE Electron. Device Lett.,2015
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