Anomalous drain‐induced barrier lowering effect of thin‐film transistors due to capacitive coupling voltage of light‐shield metal
Author:
Affiliation:
1. Department of Electronics EngineeringEwha Womans UniversitySeoul120‐750Republic of Korea
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2013.3443
Reference7 articles.
1. Polycrystalline silicon thin film transistors
2. High‐performance hydrogenated amorphous‐Si TFT for AMLCD and AMOLED applications;Chen C.;IEEE Electron Device Lett.,2005
3. Drain‐induced barrier lowering in short‐channel poly‐Si TFT after off‐bias stress using metal‐induced crystallization of amorphous silicon;Lee U.;IEEE Electron Device Lett.,2011
4. Threshold voltage in short channel polycrystalline silicon thin film transistors: influence of drain induced barrier lowering and floating body effects;Valletta A.;J. Appl. Phys.,2010
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1. Abnormal Unsaturated Output Characteristics In a-InGaZnO TFTs With Light Shielding Layer;IEEE Electron Device Letters;2019-08
2. The effect of a source-contacted light shield on the electrical characteristics of an LTPS TFT;Semiconductor Science and Technology;2017-07-03
3. P-25: The Analysis of Kink Effect in LTPS TFTs with LDD and Source Contacted Bottom Shield Metal;SID Symposium Digest of Technical Papers;2017-05
4. Anomalous capacitance characteristics of TFTs with LDD structures in the saturation region;Semiconductor Science and Technology;2016-03-29
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