Design of most-significant-bit-first serial multiplier

Author:

Lu Shih-Lien,Kenney J.

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Reference4 articles.

1. Burks, A.W., Goldstine, H.H., and von Neumann, J.: ‘Preliminary discussion of the logical design of an electronic computing machine, Part 1’, 1, (Institute for Advanced Study Princeton NJ 1946),Reprinted in von Neumann, J.: ‘Collected works’, Vol.5 (Macmillan, New York, 1964), pp. 34–79

2. The MOSIS Service, ‘CMOSN cell notebook’, Release 3.0A, 1991

3. Viewlogic‘Powerview Manual’, 1992

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1. Constant-delay MSB-first bit-serial adder;SPIE Proceedings;2002-12-01

2. Bit-serial, MSB first processing units;International Journal of Electronics;1999-06

3. Most-significant-bit-first serial/parallel multipliers;IEE Proceedings - Circuits, Devices and Systems;1998

4. Hybrid low-latency serial-parallel multiplier architecture;Electronics Letters;1998

5. Serial Architectures for Efficient Digital Fuzzy Hardware Processing;Fuzzy Hardware;1998

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