Low-glitch, high-speed charge-pump circuit for spur minimisation

Author:

Hwang I.-C.,Bae S.-G.

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Power-efficient wideband programmable pseudo differential ring oscillator CP-PLL;Microelectronics Journal;2024-09

2. An Improved Charge-Pump Design to Increase Tuning Range and Reduce Spurs in FMCW Radar Synthesizers;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06

3. A high swing charge pump with current mismatch reduction for PLL applications;IEICE Electronics Express;2021-02-25

4. Current pulse shaping technique for low spur fractional‐N phase‐locked loop;Electronics Letters;2020-03

5. Spur reduction architecture for multiphase fractional PLLs;IET Circuits, Devices & Systems;2019-11

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