Configurable multiplier blocks for embedding in FPGAs-Reference-Cited by-同舟云学术

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Configurable multiplier blocks for embedding in FPGAs

Published:1998 Issue:7 Volume:34 Page:638
ISSN:0013-5194
Container-title:Electronics Letters
language:en
Short-container-title:Electron. Lett.

Author:

Haynes S.D.,Cheung P.Y.K.

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Link

https://digital-library.theiet.org/content/journals/10.1049/el_19980501?crawler=true&mimetype=application/pdf

Reference8 articles.

1. Altera Corporation: ‘Ripple-carry adders in FLEX 8000 devices’. Application Brief 118, May 1994, Vers. 2

2. On the viability of FPGA-based integrated coprocessors

3. Hwang, K.: ‘Computer arithmetic principles, architecture, and design’, (John Wiley & Sons 1979),1st edn. p. 194–197

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A novel power-efficient multi-operand digit-multiplier using reconfiguration and clock gating;The Journal of Supercomputing;2015-04-03

2. Power-efficient pipelined reconfigurable fixed-width Baugh-Wooley multipliers;IEEE Transactions on Computers;2009-10

3. A two-level reconfigurable architecture for digital signal processing;Microelectronic Engineering;2007-02

4. Reconfigurable embedded MAC core design for low-power coarse-grain FPGA;Electronics Letters;2003

5. Morphable Multipliers;Lecture Notes in Computer Science;2002

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