Morphable Multipliers

Author:

Chiricescu Silviu,Schuette Michael,Glinton Robin,Schmit Herman

Publisher

Springer Berlin Heidelberg

Reference9 articles.

1. R. Razdan and M. D. Smith, “A high-performance microarchitecture with hardware-programmable functional units,” in Proceedings of the 27th Annual International Symposium on Microarchitecture, pp. 172–80, IEEE/ACM, Nov. 1994.

2. S. Hauck, T. Fry, M. Hosler, and J. P. Kao, “The Chimaera reconfigurable functional unit,” in IEEE Symposium on FPGAs for Custom Computing Machines, pp. 87–96, April 1997.

3. J. Hauser and J. Wawrzynek, “Garp: A MIPS processor with a reconfigurable coprocessor,” in IEEE Symposium on FPGAs for Custom Computing Machines, pp. 24–33, April 1997.

4. A. Peleg, S. Wilkie, and U. Weiser, “Intel mmx for multimedia pcs,” Communications of the ACM, vol. 40, no. 1, pp. 24–38, 1997.

5. S. D. Haynes and P. Y. K. Cheung, “Configurable multiplier blocks for embedding inFPGAs,” IEE Electronic Letters, vol. 34, pp. 638–639, Apr. 1998.

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1. Applications of Small-Scale Reconfigurability to Graphics Processors;Reconfigurable Computing: Architectures and Applications;2006

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