Modified Euclidean algorithm block for high-speed Reed-Solomon decoder
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/el_20010628?crawler=true&mimetype=application/pdf
Reference5 articles.
1. A VLSI Design of a Pipeline Reed-Solomon Decoder
2. On the VLSI design of a pipeline Reed-Solomon decoder using systolic arrays
3. Reed-Solomon VLSI codec for advanced television
4. An area-efficient VLSI architecture of a Reed-Solomon decoder/encoder for digital VCRs
5. A new scalable VLSI architecture for Reed-Solomon decoders
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