Simple digital test approach for embedded charge-pump phase-locked loops
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/el_20010914?crawler=true&mimetype=application/pdf
Reference5 articles.
1. Charge-Pump Phase-Lock Loops
2. Best, R.E.: ‘Phase-locked loops: design simulation and applications’, (McGraw-Hill 1999)
3. An effective defect-oriented BIST architecture for high-speed phase-locked loops
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1. A BIST Circuit for DLL Fault Detection;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2008-12
2. Phase Noise Model of Single Loop Frequency Synthesizer;IEEE Transactions on Broadcasting;2008-03
3. Phase-Error Measurement and Compensation in PLL Frequency Synthesizers for FMCW Sensors—I: Context and Application;IEEE Transactions on Circuits and Systems I: Regular Papers;2007-05
4. Towards generic charge-pump phase-locked loop, jitter estimation techniques using indirect on chip methods;Integration;2007-02
5. Motivations towards BIST and DfT for embedded charge-pump phase-locked loop frequency synthesisers;IEE Proceedings - Circuits, Devices and Systems;2004
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