Experimental characterisation of coaxial TSV transistor keep out zones
Author:
Affiliation:
1. Electrical and Computer Engineering DepartmentWestern New England University1215 Wilbraham RoadSpringfieldMA01119USA
2. College of Nanoscale EngineeringSUNY Polytechnic Institute257 Fuller RoadAlbanyNY12203USA
Publisher
Institution of Engineering and Technology (IET)
Subject
Condensed Matter Physics,General Materials Science,Biomedical Engineering,Bioengineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/mnl.2018.5280
Reference13 articles.
1. ‘More‐than‐Moore’ white paper;Arden W.;Int. Tech. Roadmap Semicond.,2010
2. JiangT.LuoS.: ‘3D integration‐present and future’.IEEE Tenth Electronics Packaging Technology Conf. 2008 EPTC 2008 Singapore December2008 pp.373–378
3. Homogeneous 3D Integration
4. Three-Dimensional Coaxial Through-Silicon-Via (TSV) Design
5. Feasibility of coaxial through silicon via 3D integration
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