Reduced pull-in time of phase-locked loops using a simple nonlinear phase detector
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/ip-com_19952058?crawler=true&mimetype=application/pdf
Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. PLL architecture with a composite PFD and variable loop filter;IET Circuits, Devices & Systems;2018-01-31
2. Low power PLL with reduced reference spur realized with glitch-free linear PFD and current splitting CP;Analog Integrated Circuits and Signal Processing;2017-06-21
3. A novel flash fast-locking digital phase-locked loop: design and simulations;IET Circuits, Devices & Systems;2009-10-01
4. An adjustable reset pulse phase frequency detector for phase locked loop;2009 1st Asia Symposium on Quality Electronic Design;2009-07
5. A Novel Flash Fast-Locking Digital Phase-Locked Loop;2009 Sixth International Conference on Information Technology: New Generations;2009
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