Use of unidirectional data flow in bit-level systolic array chips
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/el_19860368?crawler=true&mimetype=application/pdf
Reference7 articles.
Cited by 25 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Design of a Power Aware Systolic Array based Support Vector Machine Classifier;Advances in Systems Analysis, Software Engineering, and High Performance Computing;2015
2. Digit-Serial Systolic Architectures for Inversions over GF(2m);2006 IEEE Workshop on Signal Processing Systems Design and Implementation;2006-10
3. A class of unidirectional bit serial systolic architectures for multiplicative inversion and division over GF(2/sup m/);IEEE Transactions on Computers;2005-03
4. Digit-serial AB2 systolic architecture in GF(2m);IEE Proceedings - Circuits, Devices and Systems;2005
5. Digit-Serial AB 2 Systolic Array for Division in GF(2 m );Computational Science and Its Applications – ICCSA 2004;2004
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