Efficient replica bitline technique for variation‐tolerant timing generation scheme of SRAM sense amplifiers
Author:
Affiliation:
1. School of Electronics and Information EngineeringAnhui UniversityHefei230601People's Republic of China
Funder
National Natural Science Foundation of China
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2015.0574
Reference6 articles.
1. A replica technique for wordline and sense control in low‐power SRAM's;Amrutur B.;IEEE J. Solid‐State Circuits,1998
2. A digitized replica bitline delay technique for random‐variation‐tolerant timing generation of SRAM sense amplifiers;Niki Y.;IEEE J. Solid‐State Circuits,2011
3. A multi‐stage parallel replica‐bitline delay addition technique for reducing timing variation of SRAM sense amplifiers;Jianhui W.;IEEE. Trans. Circuits Syst. II,2014
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