High‐performance, low‐cost, and highly reliable radiation hardened latch design-Reference-Cited by-同舟云学术

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High‐performance, low‐cost, and highly reliable radiation hardened latch design

Published:2016-01 Issue:2 Volume:52 Page:139-141
ISSN:0013-5194
Container-title:Electronics Letters
language:en
Short-container-title:Electron. lett.

Author:

Yan Aibin¹,Liang Huaguo²,Huang Zhengfeng²,Jiang Cuiyun³

Affiliation:

1. School of Computer and InformationHefei University of Technology230009HefeiPeople's Republic of China

2. School of Electronic Science and Applied PhysicsHefei University of Technology230009HefeiPeople's Republic of China

3. School of MathematicsHefei University of Technology230009HefeiPeople's Republic of China

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2015.3020

Reference8 articles.

1. Single Event Transients in Digital CMOS—A Review

2. Upset hardened memory design for submicron CMOS technology

3. Low energy single event upset/single event transient‐tolerant latch for deep submicron technologies;Fazeli M.;IET Comput. Digit. Tech.,2009

4. Physics of multiple‐node charge collection and impacts on single‐event characterization and soft error rate prediction;Black J.;IEEE Trans. Nucl. Sci.,2013

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1. Design and Analysis of Latches Using RHBD Technology;2023 9th International Conference on Smart Structures and Systems (ICSSS);2023-11-23

2. Improving power and performance of on-chip network through virtual channel sharing and power gating;Integration;2023-11

3. A Non-Redundant Latch With Key-Node-Upset Obstacle of Beneficial Efficiency for Harsh Environments Applications;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-04

4. Novel radiation-hardened latch design for space-radiation environments;IEICE Electronics Express;2022-07-10

5. Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit;Electronics;2021-05-25

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