Area efficient floating‐point FFT butterfly architectures based on multi‐operand adders-Reference-Cited by-同舟云学术

Area efficient floating‐point FFT butterfly architectures based on multi‐operand adders

Published:2015-06 Issue:12 Volume:51 Page:895-897
ISSN:0013-5194
Container-title:Electronics Letters
language:en
Short-container-title:Electron. lett.

Author:

Kaivani Amir¹,Ko Seok‐Bum¹

Affiliation:

1. Electrical and Computer Engineering DepartmentUniversity of SaskatchewanSaskatoonSKCanada

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2015.0342

Reference7 articles.

1. IEEE Standards Committee:‘754‐2008 IEEE standard for floating‐point arithmetic’ August2008 pp.1–58

2. FFT implementation with fused floating‐point operations;Swartzlander E.E.;IEEE Trans. Comput.,2012

3. Kaivani A. Ko S.: ‘Floating‐point butterfly architecture based on signed‐digit representation’ IEEE Trans. Very Large Scale Integr. (VLSI) Syst. accepted for publication

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