A two-item floating point fused dot-product unit with latency reduced-Reference-Cited by-同舟云学术

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A two-item floating point fused dot-product unit with latency reduced

Published:2016 Issue:23 Volume:13 Page:20160937-20160937
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Wang Mingjiang¹,Liu De¹,Liu Ming¹,Zhao Boya¹

Affiliation:

1. Harbin Institute of Technology Shenzhen Graduate School

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/13/23/13_13.20160937/_pdf

Reference16 articles.

1. [1] J. Sohn and E. E. Swartzlander: “Improved architectures for a fused floating-point add-subtract unit,” IEEE Trans. Circuits Syst. I, Reg. Papers 59 (2012) 2285 (DOI: 10.1109/TCSI.2012.2188955).

2. [2] D. Liuet al.: “Delay-optimized floating point fused add-subtract unit,” IEICE Electron. Express 12 (2015) 20150642 (DOI: 10.1587/elex.12.20150642).

3. [3] E. E. Swartzlander and H. H. M. Saleh: “FFT implementation with fused floating-point operations,” IEEE Trans. Comput. 61 (2012) 284 (DOI: 10.1109/TC.2010.271).

4. [4] J. H. Min, et al.: “A low-power dual-path floating-point fused add-subtract unit,” 46th ACSSC Conf. Rec. (2012) 998 (DOI: 10.1109/ACSSC.2012.6489167).

5. [5] T. Yao, et al.: “A multi-path fused add-subtract unit for digital signal processing,” IEEE Int. Conf. CSAE (2012) 448 (DOI: 10.1109/CSAE.2012.6272991).

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