Programmable low-noise fast-settling fractional-N CMOS PLL with two control words for versatile applications

Author:

Rana R.S.

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Reference22 articles.

1. Agile multi-band delta-sigma frequency synthesizer architecture

2. Molnar, A. et al.: ‘A single-chip quad-band (850∕900∕1800∕1900 MHz) direct-conversion GSM∕GPRS RF transreceiver with integrated VCOs and fractional-N synthesizer’, ISSCC Digest of Technical Papers, Feb. 2002, pp. 232–233

3. A pipelined all-digital delta-sigma modulator for fractional-N frequency synthesis

4. Ajjikuttira, A. et al.: ‘A fully Integrated CMOS RFIC for Bluetooth applications’, ISSCC Digests of Technical Papers, Feb. 2001, pp. 198–199

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1. A novel pulse swallow based frequency divider circuit for a phase-locked loops;Analog Integrated Circuits and Signal Processing;2017-04-22

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