Algorithmic low power FIR cores
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/ip-cds_20030346?crawler=true&mimetype=application/pdf
Reference10 articles.
1. Algorithms for low power and high speed FIR filter realization using differential coefficients
2. Coefficient optimization for low power realization of FIR filters
3. Low power multiplication scheme for FIR filter implementation on single multiplier CMOS DSP processors
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3. A Novel Charge Recycling Design Scheme Based on Adiabatic Charge Pump;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2007-07
4. An EHW Architecture for the Design of Unconstrained Low-Power FIR Filters for Sensor Control Using Custom-Reconfigurable Technology;2005 NASA/DoD Conference on Evolvable Hardware (EH'05)
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