Optimized Voter Circuit for Fault Tolerant Implementation in TMR

Author:

Gomes Emmanuel Prince,Saha Ankita,Beulet Augusta Sophy

Publisher

Elsevier BV

Reference10 articles.

1. Fault-Tolerant Digital Filters on FPGA using Hardware Redundancy techniques;Prasanth Mallavarapu;International Conference on electronics, Communication and Aerospace Technology ICECA. International Conference on Sustainable Computing in Science, Technology & Management,2017

2. Design of a novel fault-tolerant voter circuit for TMR implementation to improve reliability in digital circuits;R V Kshirsagar;Microelectronics Reliability Received in revised form 21,2009

3. Fault Tolerant System for FPGA Using Simulation Based Fault Injection Technique;Tian Ban;Nikhila C. Admane and Dinesh R. Rotake,2010

4. On-Line Self-Healing of Circuits Implemented on Reconfigurable FPGAs;G Manuel;13th IEEE International On-Line Testing Symposium,2007

5. A Comparison of TMR With Alternative Fault-Tolerant Design Techniques for FPGAs;Keith S Morgan;IEEE Transactions on Nuclear Science,2007

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