1. Low voltage CMOS timing generator using array of digital delay lock loops;S Balaji;Circuits and Systems (MWSCAS) 2012 IEEE 55th International Midwest Symposium on,2012
2. High-resolution time-todigital converter utilising fractional difference conversion scheme;N Xing;Electronics Letters,2010
3. Voltage controlled current starved delay cell for Positron Emission Tomography specific DLL based high precision TDC implementation;S A Mondal;Computers and Devices for Communication (CODEC) 2012 5th International Conference on,2012
4. A Brief Introduction to Timeto-Digital and Digital-to-Time Converters;G W Roberts;IEEE Transactions on Circuits and Systems II: Express Briefs,2010
5. A digital phase-locked loop with calibrated coarse and stochastic fine TDC;A Samarah;Proceedings of the IEEE 2012 Custom Integrated Circuits Conference,2012