Improving Cache Energy Efficiency for Green Computing
Author:
Affiliation:
1. Iowa State University, USA
Abstract
Publisher
IGI Global
Reference27 articles.
1. IATAC: a smart predictor to turn-off L2 cache lines
2. Albonesi, D. H. (1999). Selective cache ways: On-demand cache resource allocation. 32nd Annual International Symposium on Microarchitecture, 248-259.
3. Chang, Jonathan and Ming Huang and Shoemaker, J. and Benoit, J. and Chen, Szu-Liang and Chen, Wei and Chiu, Siufu and Ganesan, Raghuraman and Leong, G. and Lukka, Venkata and Rusu, S. and Srivastava, D. (2007). The 65-nm 16-MB shared on-die L3 cache for the dual-core Intel Xeon processor 7100 series. IEEE Journal of Solid-State Circuits, 42(4), 846-852.
4. The Green500 List: Encouraging Sustainable Supercomputing
5. Flautner, K., Kim, N. S., Martin, S., Blaauw, D., & Mudge, T. (2002). Drowsy caches: simple techniques for reducing leakage power. Annual International Symposium on Computer Architecture, 148-157.
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