The Ultimate Data Flow for Ultimate Super Computers-on-a-Chip-Reference-Cited by-同舟云学术

The Ultimate Data Flow for Ultimate Super Computers-on-a-Chip

Published:2021 Issue: Volume: Page:312-318
ISSN:2327-3453
Container-title:Advances in Systems Analysis, Software Engineering, and High Performance Computing
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Author:

Milutinović Veljko¹,Kotlar Miloš²,Ratković Ivan³^ORCID,Korolija Nenad⁴,Djordjevic Miljan⁵,Yoshimoto Kristy¹,Valero Mateo⁶

Affiliation:

1. Indiana University, USA

2. School of Electrical Engineering, University of Belgrade, Serbia

3. Esperanto Technologies, Serbia

4. Independent Researcher, Serbia

5. University of Belgrade, Serbia

6. BSC, Spain

Abstract

This chapter starts from the assumption that near future 100BTransistor SuperComputers-on-a-Chip will include N big multi-core processors, 1000N small many-core processors, a TPU-like fixed-structure systolic array accelerator for the most frequently used machine learning algorithms needed in bandwidth-bound applications, and a flexible-structure reprogrammable accelerator for less frequently used machine learning algorithms needed in latency-critical applications. The future SuperComputers-on-a-Chip should include effective interfaces to specific external accelerators based on quantum, optical, molecular, and biological paradigms, but these issues are outside the scope of this chapter.

Publisher

IGI Global

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