Merging control-flow and dataflow architectures on a single chip

Abstract

Computing power rises predominantly by increasing the number of cores in modern processors and the number of processors in cluster and cloud architectures. Along with increasing processing power, high-performance computing requirements also rise. The majority of the computing infrastructure includes control-flow processors that are based on the von Neumann paradigm. On the contrary, the principle of dataflow architectures is based on the data flowing through the already configured hardware. Recent research has proposed hybrid architectures, where both control-flow and dataflow hardware would exist on the same chip die. This article proposes a new hybrid control-flow and dataflow architecture where the control-flow hardware resembles modern graphical cards with thousands of cores and each GPU core has a reasonable amount of data-flow hardware. In this way, the advantages of dataflow architecture are exploited, including faster processing of high-performance computing algorithms and lower power consumption, while the conventional problem of communicating between control-flow and dataflow architectures is minimized. The proposed architecture is tested by analyzing the conjugate gradient method executed on both control-flow and dataflow hardware. The execution of the algorithm is divided onto GPU cores, and the execution of repeated instructions on each GPU core is delegated to the assigned dataflow hardware. The results indicate that it is possible to accelerate the execution of algorithms using the proposed architecture.