Machine Learning Optimization Techniques for 3D IC Physical Design

Abstract

The importance and growth of the digital IC have become more popular because of parameters such as small feature size, high speed, low cost, less power consumption, and temperature. There have been various techniques and methodologies developed so far using different optimization algorithms and data structures based on the dimensions of the IC to improve these parameters. All these existing algorithms illustrate explicit advantages in optimizing the chip area, maximum temperature of the chip, and wire length. Though there are some advantages in these traditional algorithms, there are few demerits such as execution time, integration, and computational complexity due to the necessity of handling large number of data. Machine learning techniques produce vibrant results in such fields where it is required to handle big data in order to optimize the scaling parameters of IC design. The objective of this chapter is to give an elaborate idea of applying machine learning techniques using Bayesian theorem to create automation tool for VLSI 3D IC design steps.