Affiliation:
1. Department of Computer Science and Engineering, Frederick University, Nicosia, Cyprus
2. School of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece
Abstract
This paper presents a framework for high-level exploration, Register Transfer-Level (RTL) design and rapid prototyping of Network-on-Chip (NoC) architectures. From the high-level exploration, a selected NoC topology is derived, which is then implemented in RTL using an automated design flow. Furthermore, for verification purposes, appropriate self-checking testbenches for the verification of the RTL and architecture files for the semi-automatic implementation of the system in Xilinx EDK are also generated, significantly reducing design and verification time, and therefore Non-Recurring Engineering (NRE) cost. Simulation and FPGA implementation results are given for four case studies multimedia applications, proving the validity of the proposed approach.
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1. The SYSMANTIC NoC Design and Prototyping Framework;Designing 2D and 3D Network-on-Chip Architectures;2013-10-09