Cu Bump Interconnections in 20.MU.m-Pitch at Low Temperature Utilizing Electroless Tin-Plating on 3D Stacked LSI.-Reference-Cited by-同舟云学术

Cu Bump Interconnections in 20.MU.m-Pitch at Low Temperature Utilizing Electroless Tin-Plating on 3D Stacked LSI.

Published:2003 Issue:2 Volume:36 Page:119-125
ISSN:0021-9592
Container-title:JOURNAL OF CHEMICAL ENGINEERING OF JAPAN
language:en
Short-container-title:J. Chem. Eng. Japan

Author:

Tomita Yoshihiro¹,Morifuji Tadahiro¹,Tomisaka Manabu¹,Sunohara Masahiro¹,Nemoto Yoshihiko¹,Sato Tomotoshi¹,Takahashi Kenji¹,Bonkohara Manabu¹

Affiliation:

1. Association of Super-Advanced Electronics Technologies (ASET), Electronic System Integration Technology Research Department, Tsukuba Research Center, Tsukuba Center Inc.

Publisher

Society of Chemical Engineers, Japan

Subject

General Chemical Engineering,General Chemistry

Link

http://www.jstage.jst.go.jp/article/jcej/36/2/36_2_119/_pdf

Reference11 articles.

1. Aging studies of Cu-Sn intermetallic compounds in annealed surface mount solder joints

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